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preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 1 copyright ? cirrus logic, inc. 2000 (all rights reserved) p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.cirrus.com cs4391 24-bit, 192 khz stereo dac with volume control features l complete stereo dac system: interpolation, d/a, output analog filtering l 108 db dynamic range l 94 db thd+n l direct stream digital mode l low clock jitter sensitivity l +5 v to +3 v power supply l atapi mixing l on-chip digital de-emphasis for 32, 44.1, and 48 khz l volume control with soft ramp C 119 db attenuation C 1 db step size C zero crossing click-free transitions l 36 mw with 3 v supply l direct interface with 5 v to 1.8 v logic description the cs4391 is a complete stereo digital-to-analog sys- tem including digital interpolation, fourth-order delta- sigma digital-to-analog conversion, digital de-emphasis, volume control, channel mixing and analog filtering. the advantages of this architecture include: ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and tempera- ture and a high tolerance to clock jitter. the cs4391 accepts pcm data at sample rates from 2 khz to 192 khz, dsd audio data, consumes very little power and operates over a wide power supply range. these features are ideal for dvd, a/v receivers, cd and set-top box systems. ordering information CS4391-KZ 20-pin tssop -10 to 70 c cdb4391 evaluation board i lrck sdata (sda/cdin) mclk amutec aouta- aoutb- serial port interpolation interpolator (control port) ds dac dac external analog filter analog filter ds mute control filter filter rst sclk volume control volume control mixer (scl/cclk) (ad0/cs ) aouta+ aoutb+ cmout reference filt+ bmutec m1 m3 m2 mode select m0 apr 00 ds335pp3
cs4391 2 ds335pp3 table of contents 1. characteristics/specifications .......................................................................... 5 analog characteristics...................................................................................... 5 digital characteristics....................................................................................... 7 absolute maximum ratings ................................................................................. 7 recommended operating conditions............................................................. 7 switching characteristics - pcm modes....................................................... 8 switching characteristics - dsd ..................................................................... 9 switching characteristics - i 2 c control port ........................................ 10 switching characteristics - spi control port ....................................... 11 2. typical connection diagrams ............................................................................ 12 3. register quick reference ................................................................................... 14 3.1 mode control 1 (address 01h)................................................................................ 14 3.2 volume and mixing control (address 02h) ............................................................. 15 3.3 channel a volume control (address 03h).............................................................. 15 3.4 channel b volume control (address 04h).............................................................. 15 3.5 mode control 2 (address 05h)................................................................................ 16 4. register description ............................................................................................. 17 4.1 mode control 1 - address 01h................................................................................ 17 4.1.1 auto-mute (bit 7) .............................................................................17 4.1.2 digital interface formats (bits 6:4) ..................................................17 4.1.3 de-emphasis control (bits 3:2) .......................................................17 4.1.4 functional mode (bits 1:0) ..............................................................17 4.2 volume and mixing control (address 02h)............................................................. 18 4.2.1 channel a volume = channel b volume (bit 7) ..............................18 4.2.2 soft ramp or zero cross enable (bits 6:5) .....................................18 4.2.3 atapi channel mixing and muting (bits 4:0) ..................................18 4.3 channel a volume control - address 03h.............................................................. 18 4.4 channel b volume control - address 04h.............................................................. 19 4.4.1 mute (bit 7) ......................................................................................19 4.4.2 volume control (bits 6:0) ................................................................19 4.5 mode control 2 - address 05h................................................................................ 19 4.5.1 invert signal polarity (bits 7:6) ........................................................19 4.5.2 control port enable (bit 5) ..............................................................19 4.5.3 power down (bit 4) .........................................................................19 4.5.4 amutec = bmutec (bit 3) ...........................................................19 4.5.5 freeze (bit 2) ..................................................................................20 4.5.6 master clock divide (bit 1) ..............................................................20 5. pin description - pcm data mode ........................................................................ 21 reset - rst .................................................................................................................. 21 interface power - vl..................................................................................................... 21 contacting cirrus logic support for a complete listing of direct sales, distributor, and sales representative contacts, visit the cirrus logic web site at: http://www.cirrus.com/corporate/contacts/ i 2 c is a registered trademark of philips semic onductors. preliminary product information describes products which are in production, but for which full characterization data is not yet available. advance product infor- mation describes products which are in development and subject to development changes. cirrus logic, inc. has made best effort s to ensure that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provi d ed as is without warranty of any kind (express or implied). no responsibility is assumed by cirrus logic, inc. for the use of this information, nor for inf ringements of patents or other rights of third parties. this document is the property of cirrus logic, inc. and implies no license under patents, copyrights, tradem arks, or trade secrets. no part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electron ic, mechanical, photographic, or otherwise) without the prior written consent of cirrus logic, inc. items from any cirrus logic website or disk may be printed for use by the user. however, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form o r by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of cirrus logic, inc.furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of cirrus logic, inc. the names of products of cirrus logic, inc. or ot her vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. a list of cirrus logic, inc. trade- marks and service marks can be found at http://www.cirrus.com.
cs4391 ds335pp3 3 serial audio data - sdata ...........................................................................................21 serial clock - sclk ......................................................................................................22 left / right clock - lrck ..............................................................................................22 master clock - mclk ....................................................................................................22 mode select - m3, m2, m1 and m0 (stand-alone mode) .............................................22 mode select - m3 (control port mode) ........................................................................22 serial control interface clock - scl/cclk (control port mode) .................................23 serial control data i/o - sda/cdin (control port mode) .............................................23 address bit / chip select - ad0 / cs (control port mode)...........................................23 positive voltage reference - filt+ ..............................................................................23 common mode voltage - cmout ................................................................................23 channel a and channel b mute control - amutec and bmutec .............................23 differential analog output - aoutb+, aoutb- and aouta+, aouta-......................24 analog ground - agnd ................................................................................................24 analog power - va........................................................................................................24 6. pin description - dsd mode ....................................................................................25 dsd audio data - dsd_a and dsd_b.........................................................................25 dsd mode - dsd_mode ...............................................................................................25 master clock - mclk ....................................................................................................25 dsd serial clock - dsd_sclk ...................................................................................25 7. applications .............................................................................................................. .32 7.1 recommended power-up sequence for hardware mode ....................................32 7.2 recommended power-up sequence and access to control port mode ..............32 7.3 analog output and filtering ..................................................................................32 8. control port interface ........................................................................................33 8.1 spi mode ..............................................................................................................33 8.2 i2c mode ..............................................................................................................33 9. parameter definitions ...........................................................................................37 total harmonic distortion + noise (thd+n) .................................................................37 dynamic range.............................................................................................................37 interchannel isolation ....................................................................................................37 interchannel gain mismatch .........................................................................................37 gain error..................................................................................................................... .37 gain drift ..................................................................................................................... ..37 10. references ............................................................................................................... 37 11. package dimensions ...........................................................................................38
cs4391 4 ds335pp3 list of tables figure:1. digital interface formats - pcm modes ....................................................................... 26 figure:2. digital interface formats - dsd mode ......................................................................... 26 figure:3. de-emphasis mode selection ..................................................................................... 26 figure:4. functional mode selection .......................................................................................... .26 figure:5. soft cross or zero cross mode selection ................................................................... 26 figure:6. atapi decode ....................................................................................................... ...... 27 figure:7. digital volume control ............................................................................................. .... 27 figure:8. single speed (4 to 50 khz sample rates) common clock frequencies ...................... 28 figure:9. double speed (50 to 100 khz sample rates) common clock frequencies ................ 28 figure:10. quad speed (100 to 200 khz sample rates) common clock frequencies .............. 28 figure:11. single speed (4 to 50 khz) digital interface format, stand-alone mode options ..... 28 figure:12. single speed only (4 to 50 khz) de-emphasis, stand-alone mode options ............ 28 figure:13. double speed (50 to 100 khz) digital interface format, stand-alone mode options 28 figure:14. quad speed (100 to 200 khz) digital interface format, stand-alone mode options 29 figure:15. direct stream digital (dsd), stand-alone mode options .......................................... 29 figure:16. memory address pointer (map) ................................................................................ 34 list of figures figure 1. serial mode input timing ............................................................................................. .... 8 figure 2. direct stream digital - serial audio input timing............................................................. 9 figure 3. i 2 c control port timing .................................................................................................. 10 figure 4. spi control port timing .............................................................................................. ... 11 figure 5. typical connection diagram - pcm mode..................................................................... 12 figure 6. typical connection diagram - dsd mode ..................................................................... 13 figure 7. format 0, left justified up to 24-bit data....................................................................... 30 figure 8. format 1, i2s up to 24-bit data ..................................................................................... 3 0 figure 9. format 2, right justified 16-bit data ............................................................................. 30 figure 10. format 3, right justified 24-bit data ........................................................................... 30 figure 11. format 4, right justified 20-bit data. (available in control port mode only).............. 31 figure 12. format 5, right justified 18-bit data. (available in control port mode only)............... 31 figure 13. de-emphasis curve ................................................................................................... .. 31 figure 14. atapi block diagram ................................................................................................. .31 figure 15. cs4391 output filter ................................................................................................ ... 32 figure 16. control port timing, spi mode .................................................................................... 34 figure 17. control port timing, i 2 c mode ..................................................................................... 34 figure 18. single-speed frequency response ............................................................................ 35 figure 19. single-speed transition band ..................................................................................... 35 figure 20. single-speed transition band ..................................................................................... 35 figure 21. single-speed stopband rejection ............................................................................... 35 figure 22. double-speed frequency response ........................................................................... 35 figure 23. double-speed transition band .................................................................................... 35 figure 24. double-speed transition band .................................................................................... 36 figure 25. double-speed stopband rejection.............................................................................. 36
cs4391 ds335pp3 5 1. characteristics/specifications analog characteristics (t a = 25 c; logic "1" = vl = va; logic "0" = agnd; full-scale out- put sine wave, 997 hz; mclk = 12.288 mhz; sclk = 3.072 mhz, sample rate = 48, 96 or 192 khz, 24-bit data, measurement bandwidth 10 hz to 20 khz, unless otherwise specified. test load r l = 5 k w , c l = 10 pf) parameter va = 3 v va = 5 v symbol min typ max min typ max unit dynamic performance dynamic range (note 17) unweighted a-weighted 40 khz bandwidth a-weighted 97 100 - 102 105 99 - - - 100 103 - 105 108 102 - - - db db db total harmonic distortion + noise (note 17,2) 0 db -20 db -60 db thd+n - - - -94 -82 -42 -89 - -37 - - - -94 -85 -45 -89 - -40 db db db idle channel noise / signal-to-noise ratio - 105 - - 108 - db interchannel isolation (1 khz) - 100 - - 100 - db power supplies power supply current normal operation power-down state i a + i l i a + i l - - 12 30 tbd - - - 17 60 tbd - ma m a power dissipation normal operation power-down - - 36 0.09 tbd - - - 85 0.3 tbd - mw mw power supply rejection ratio (1 khz) (note 3) (60 hz) psrr - - 60 40 - - - - 60 40 - - db db parameter symbol min typ max units analog output full scale differential output voltage tbd 1.1va tbd vpp common mode voltage cmout - 0.5va - vdc interchannel gain mismatch - 0.1 - db gain drift - 100 - ppm/c ac-load resistance r l 5- -k w load capacitance c l --100pf
cs4391 6 ds335pp3 analog characteristics (continued) notes: 17. triangular pdf dithered data. 18. thd+n specifications for 48 khz sample rates are made over a 20 khz bandwidth. 19. valid with the recommended capacitor values on filt+ and cmout as shown in figure 1. increasing the capacitance will also increase the psrr. 20. response is clock dependent and will scale with fs. note that the response plots (figures 17-24) have been normalized to fs and can be de-normalized by multiplying the x-axis scale by fs. 21. for single-speed mode, the measurement bandwidth is 0.5465 fs to 3 fs. for double-speed mode, the measurement bandwidth is 0.577 fs to 1.4 fs. parameter symbol min typ max unit combined digital and on-chip analog filter response - single speed mode passband (note 3) to -0.05 db corner to -3 db corner 0 0 - - .4535 .4998 fs fs frequency response 10 hz to 20 khz -.02 - +.035 db stopband .5465 - - fs stopband attenuation (note 5) 50 - - db group delay tgd - 9/fs - s passband group delay deviation 0 - 20 khz - 0.36/fs - s de-emphasis error (relative to 1 khz) control port mode fs = 32 khz fs = 44.1 khz fs = 48 khz stand-alone mode fs = 32 khz fs = 44.1 khz fs = 48 khz - - - - - - - - - - - - +.2/-.1 +.05/-.14 +0/.22 tbd +.05/-.14 tbd db db db db db db combined digital and on-chip analog filter response - double speed mode passband (note 4) to -0.1 db corner to -3 db corner 0 0 - - .4621 .4982 fs fs frequency response 10 hz to 20 khz -0.1 - 0 db stopband .577 - - fs stopband attenuation (note 5) 55 - - db group delay tgd - 9/fs - s passband group delay deviation 0 - 20 khz - 0.23/fs - s on-chip analog filter response - quad speed mode passband (note 4) to -3 db corner 0 - 0.25 fs frequency response 10 hz to 20 khz -0.7 - 0 db on-chip analog filter response - dsd mode passband (note 4) to -3 db corner 0 - 1.0 fs frequency response 10 hz to 20 khz -0.7 - 0 db
cs4391 ds335pp3 7 digital characteristics (t a = 25 c) absolute maximum ratings (agnd = 0 v; all voltages with respect to ground.) warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (agnd = 0v; all voltages with respect to ground.) parameters symbol min typ max units high-level input voltage v ih 70% - - vl low-level input voltage v il - 20% vl input leakage current i in --10 m a input capacitance - 8 - pf maximum mutec drive current - 3 - ma parameters symbol min max units dc power supply va vl -0.3 -0.3 6.0 va v v input current, any pin except supplies i in - 10 ma digital input voltage v ind -0.3 vl+0.4 v ambient operating temperature (power applied) t a -55 125 c storage temperature t stg -65 150 c parameters symbol min typ max units dc power supply va vl 2.7 1.8 5.0 - 5.5 va v v
cs4391 8 ds335pp3 switching characteristics - pcm modes (t a = -10 to 70 c; vl = 5.5 to 1.8 volts; inputs: logic 0 = 0 v, logic 1 = vl, cl = 20 pf) notes: 22. this serial clock is available only in control port mode when the mclk divide bit is enabled. parameters symbol min typ max units input sample rate fs 4 - 200 khz lrck duty cycle 45 50 55 % mclk duty cycle 405060 % sclk frequency - -mclk/2hz sclk frequency note 22 - -mclk/4hz sclk rising to lrck edge delay t slrd 20 - - ns sclk rising to lrck edge setup time t slrs 20 - - ns sdata valid to sclk rising setup time t sdlrs 20 - - ns sclk rising to sdata hold time t sdh 20 - - ns slrs t slrd t sdlrs t sdh t sdata sclk lrck figure 1. serial mode input timing
cs4391 ds335pp3 9 switching characteristics - dsd (t a = -10 to 70 c; logic 0 = agnd = dgnd; logic 1 = vl = 5.5 to 1.8 volts; c l =20pf) parameter symbol min typ max unit mclk duty cycle 405060 % sclk pulse width low t sclkl tbd - - ns sclk pulse width high t sclkh tbd - - ns sclk period t sclkw tbd --ns sdin valid to sclk rising setup time t sdlrs tbd - - ns sclk rising to sdin hold time t sdh tbd - - ns sclkh t sclkl t sdata sclk sdlrs t sdh t figure 2. direct stream digital - serial audio input timing
cs4391 10 ds335pp3 switching characteristics - i 2 c control port (t a = 25 c; vl = 5.5 to 1.8 volts; inputs: logic 0 = agnd, logic 1 = vl, c l = 30 pf) notes: 23. data must be held for sufficient time to bridge the 300 ns transition time of scl. parameter symbol min max unit i 2 c ? mode scl clock frequency f scl -100khz rst rising edge to start t irs 500 - ns bus free time between transmissions t buf 4.7 - s start condition hold time (prior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time from scl falling (note 23) t hdd 0-s sda setup time to scl rising t sud 250 - ns rise time of both sda and scl lines t r -1s fall time of both sda and scl lines t f -300ns setup time for stop condition t susp 4.7 - s t buf t hdst t hdst t low t r t f t hdd t high t sud t sust t susp stop start start stop repeated sda scl t irs rst figure 3. i 2 c control port timing
cs4391 ds335pp3 11 switching characteristics - spi control port (t a = 25 c; vl = 5.5 to 1.8 volts; inputs: logic 0 = agnd, logic 1 = vl, c l = 30 pf) notes: 24. t spi only needed before first falling edge of cs after rst rising edge. t spi = 0 at all other times. 25. data must be held for sufficient time to bridge the transition time of cclk. 26. for f sck < 1 mhz parameter symbol min max unit spi mode cclk clock frequency f sclk -6mhz rst rising edge to cs falling t srs 500 - ns cclk edge to cs falling (note 24) t spi 500 - ns cs high time between transmissions t csh 1.0 - s cs falling to cclk edge t css 20 - ns cclk low time t scl 66 - ns cclk high time t sch 66 - ns cdin to cclk rising setup time t dsu 40 - ns cclk rising to data hold time (note 25) t dh 15 - ns rise time of cclk and cdin (note 26) t r2 -100ns fall time of cclk and cdin (note 26) t f2 -100ns t r2 t f2 t dsu t dh t sch t scl cs cclk cdin t css t csh t spi t srs rst figure 4. spi control port timing
cs4391 12 ds335pp3 2. typical connection diagrams sclk audio data processor * external clock mclk agnd aoutb+ cs4391 sdata va aoutb- +5v to +3v analog mode select m1 (sda/ cdin ) m0 (ad0/cs) aouta- aouta+ analog conditioning & mute analog conditioning & mute 17 19 18 14 15 16 1 3 4 5 8 9 10 m2 (scl/cclk) lrck 1.0 m f + rst 6 m3 7 12 1.0 f 0.1 f 1.0 f 11 filt+ 0.1 f + + cmout bmutec 13 amutec 20 (control port) * 2 vl logic power +5v to 1.8v 0.1 f figure 5. typical connection diagram - pcm mode * a high logic level for all digital inputs should not exceed vl.
cs4391 ds335pp3 13 dsd_b audio data processor * external clock mclk agnd aoutb+ cs4391 dsd_a va aoutb- +5v to +3v analog mode select m1 (sda/ cdin ) m0 (ad0/cs) aouta- aouta+ vl analog conditioning & mute analog conditioning & mute 17 19 18 14 15 16 1 2 3 4 7 8 9 10 m2 (scl/cclk) dsd_clk 1.0 m f + rst 6 12 1.0 f 0.1 f 1.0 f 11 filt+ 0.1 f + + cmout bmutec 13 amutec 20 (control port) 5 dsd_mode logic power +5v to 1.8v 0.1 f figure 6. typical connection diagram - dsd mode * a high logic level for all digital inputs should not exceed vl.
cs4391 14 ds335pp3 3. register quick reference ** default ==> bit status after power-up-sequence or reset** 3.1 mode control 1 (address 01h) amute (auto-mute) default = 1. 0 - disabled 1 - enabled dif2, dif1 and dif0 (digital interface format - pcm modes). see table 1 default = 0. 000 - format 0, left justified, up to 24-bit data 001 - format 1, i 2 s, up to 24-bit data 010 - format 2, right justified, 16-bit data 011 - format 3, right justified, 24-bit data 100 - format 4, right justified, 20-bit data 101 - format 5, right justified, 18-bit data 110 - reserved 111 - reserved dif2, dif1 and dif0 (digital interface format - dsd mode only). seetable 2 default = 0. 000 - format 0, 64x oversampled dsd data with a 4x mclk to dsd data rate 001 - format 1, 64x oversampled dsd data with a 6x mclk to dsd data rate 010 - format 2, 64x oversampled dsd data with a 8x mclk to dsd data rate 011 - format 3, 64x oversampled dsd data with a 12x mclk to dsd data rate 100 - format 4, 128x oversampled dsd data with a 2x mclk to dsd data rate 101 - format 5, 128x oversampled dsd data with a 3x mclk to dsd data rate 110 - format 6, 128x oversampled dsd data with a 4x mclk to dsd data rate 111 - format 7, 128x oversampled dsd data with a 6x mclk to dsd data rate dem1, dem0 (de-emphasis mode). see table 3 default = 00. 00 - no de-emphasis 01 - 44.1 khz de-emphasis 10 - 48 khz de-emphasis 11 - 32 khz de-emphasis fm1, fm0 (functional mode). see table 4 default = 00. 00 - single-speed mode (4 to 50 khz sample rates) 01 - double-speed mode (50 to 100 khz sample rates) 10 - quad-speed mode (100 to 200 khz sample rates) 11 - direct stream digital mode 76543210 amute dif2 dif1 dif0 dem1 dem0 fm1 fm0 10000000
cs4391 ds335pp3 15 3.2 volume and mixing control (address 02h) a = b (channel a volume = channel b volume) default = 0. 0 - aouta volume is determined by register 03h and aoutb volume is determined by reg- ister 04h. 1 - aouta and aoutb volumes are determined by register 03h and register 04h is ig- nored. soft & zero cross (soft control and zero cross detection control) default = 10. softzero crossmode 00 changes take effect immediately 01 changes take effect on zero crossings 10 changes take effect with a soft ramp (default) 11 changes take effect in 1/8 db steps on each zero crossing atapi 0-4 (channel mixing and muting). seetable 6 default = 01001, (stereo) aouta = left channel aoutb = right channel 3.3 channel a volume control (address 03h) see channel b volume control (address 04h) 3.4 channel b volume control (address 04h) mute default = 0 0 - disabled 1 - enabled volume default = 0 (refer to table 7) 76543210 a = b soft zero cross atapi4 atapi3 atapi2 atapi1 atapi0 01001001 76543210 mute vol6 vol5 vol4 vol3 vol2 vol1 vol0 00000000
cs4391 16 ds335pp3 3.5 mode control 2 (address 05h) invert_a (invert channel a) default = 0. 0 - disabled 1 - enabled invert_b (invert channel b) default = 0. 0 - disabled 1 - enabled cpen (control port enable) default = 0 0 - disabled (stand-alone mode) 1 - enabled (control port mode) pdn (power-down) default =1. 0 - disabled 1 - enabled mutec a=b default = 0. 0 - disabled 1 - enabled freeze default = 0. 0 - disabled 1 - enabled mclk divide default = 0. 0 - disabled 1 - enabled 76543210 invert_a invert_b cpen pdn mutec a = b freeze mclk divide reserved 00110000
cs4391 ds335pp3 17 4. register description ** all register access is r/w in i 2 c mode and write only in spi mode ** 4.1 mode control 1 - address 01h 4.1.1 auto-mute (bit 7) function: the digital-to-analog converter output will mute following the reception of 8192 consecutive audio samples of static 0 or -1. a single sample of non-static data will release the mute. detection and muting is done independently for each channel. (however, auto-mute detection and muting can be- come dependent on either channel if the mute a = b function is enabled.) the common mode on the output will be retained and the mute control pin for that channel will go active during the mute period. the muting function is effected, similar to volume control changes, by the soft and zero cross bits in the volume and mixing control register. 4.1.2 digital interface formats (bits 6:4) function: pcm mode - the required relationship between the left/right clock, serial clock and serial data is defined by the digital interface format and the options are detailed in table 2 and figures 6-24. dsd mode - the relationship between the oversampling ratio of the dsd audio data and the required master clock to dsd data rate is defined by the digital interface format pins. note that the functional mode registers must be set to dsd mode. see table 1 (pcm modes) see table 2 (dsd mode) 4.1.3 de-emphasis control (bits 3:2) function: implementation of the standard 15 m s/50 m s digital de-emphasis filter response, figure 12, requires reconfiguration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 khz sample rates. note: de-emphasis is available only in single-speed mode. see table 3 4.1.4 functional mode (bits 1:0) function: selects the required range of input sample rates or dsd mode. see table 4 76543210 amute dif2 dif1 dif0 dem1 dem0 fm1 fm0
cs4391 18 ds335pp3 4.2 volume and mixing control (address 02h) 4.2.1 channel a volume = channel b volume (bit 7) function: the aouta and aoutb volume levels are independently controlled by the a and the b channel vol- ume control bytes when this function is disabled. the volume on both aouta and aoutb are de- termined by the a channel volume control byte and the b channel byte is ignored when this function is enabled. 4.2.2 soft ramp or zero cross enable (bits 6:5) function: soft ramp enable soft ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 db steps, from the current level to the new level at a rate of 1db per 8 left/right clock periods. zero cross enable zero cross enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. the requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encounter a zero crossing. the zero cross function is independently monitored and implemented for each channel. soft ramp and zero cross enable soft ramp and zero cross enable dictates that signal level changes, either by attenuation changes or muting, will occur in 1/8 db steps and be implemented on a signal zero crossing. the 1/8 db level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encounter a zero crossing. the zero cross function is independently monitored and implemented for each channel. see table 5 4.2.3 atapi channel mixing and muting (bits 4:0) function: the cs4391 implements the channel mixing functions of the atapi cd-rom specification. see table 6 4.3 channel a volume control - address 03h see 4.4 channel b volume control - address 04h 76543210 a = b soft zero cross atapi4 atapi3 atapi2 atapi1 atapi0
cs4391 ds335pp3 19 4.4 channel b volume control - address 04h 4.4.1 mute (bit 7) function: the digital-to-analog converter output will mute when enabled. the common mode voltage on the output will be retained. the muting function is effected, similiar to attenuation changes, by the soft and zero cross bits in the volume and mixing control register. the mutec pin for that channel will go active during the mute period if the mute function is enabled. both the amutec and bmutec will go active if either mute register is enabled and the mutec a = b bit (register 5) is enabled. 4.4.2 volume control (bits 6:0) function: the digital volume control allows the user to attenuate the signal in 1 db increments from 0 to -119 db. volume settings are decoded as shown in table 7. the volume changes are implemented as dictated by the soft and zero cross bits in the volume and mixing control register. all volume settings less than - 119 db are equivalent to enabling the mute bit. 4.5 mode control 2 - address 05h 4.5.1 invert signal polarity (bits 7:6) function: when set, this bit inverts the signal polarity. 4.5.2 control port enable (bit 5) function: this bit defaults to 0, allowing the device to power-up in stand-alone mode. the control port mode can be accessed by setting this bit to 1. this will allow the operation of the device to be controlled by the registers and the pin definitions will conform to control port mode. to accomplish a clean power- up, the user should write 11h to register 5 within 10 ms following the release of reset. 4.5.3 power down (bit 4) function: the device will enter a low-power state whenever this function is activated. the power-down bit de- faults to enabled on power-up and must be disabled before normal operation will begin. the contents of the control registers are retained when the device is in power-down. 4.5.4 amutec = bmutec (bit 3) function: when this function is enabled, the individual controls for amutec and bmutec are internally con- nected through a and gate prior to the output pins. therefore, the external amutec and bmutec pins will go active only when the requirements for both amutec and bmutec are valid. 76543210 mute vol6 vol5 vol4 vol3 vol2 vol1 vol0 76543210 invert_a invert_b cpen pdn mutec a = b freeze mclk divide reserved
cs4391 20 ds335pp3 4.5.5 freeze (bit 2) function: this function allows modifications to the registers without the changes being taking effect until freeze is disabled. to make multiple changes in the control port registers take effect simultaneously, set the freeze bit, make all register changes, then disable the freeze bit. 4.5.6 master clock divide (bit 1) function: this function allows the user to select an internal divide by 2 of the master clock. this selection is required to access the higher master clock rates as shown in table 9.
cs4391 ds335pp3 21 5. pin description - pcm data mode reset - rst pin 1, input function: hardware mode: the device enters a low power mode and the internal state machine is reset to the de- fault setting when low. when high, the device becomes operational. control port mode: the device enters a low power mode and all internal registers are reset to the default settings, including the control port, when low. when high, the control port becomes operational and the pdn bit must be cleared before normal operation will occur. the control port can not be accessed when reset is low. the control port enable bit must also be enabled after a device reset. rst is required to remain low until the power supplies and clocks are applied and stable. interface power - vl pin 2, input function: digital interface power supply. typically 1.8 to 5.0 vdc. the voltage on this pin determines the logic level high threshold for the digital inputs. the voltage on vl is the maximum allowable input level for all digital inputs. serial audio data - sdata pin 3, input function: two's complement msb-first serial data is input on this pin. the data is clocked into sdata via the serial clock and the channel is determined by the left/right clock. the required relationship between the left/right clock, serial clock and serial data is defined by the mode control byte in control port mode or the mode pins in hardware mode. the options are detailed in figures 6-24. reset rst amutec channel a mute control logic voltage vl aouta- differential output serial data sdata aouta+ differential output serial clock sclk va analog power left/right clock lrck agnd analog ground master clock mclk aoutb+ differential output see description m3 aoutb- differential output see description ( scl/cclk) m2 bmutec channel b mute control see description ( sda/cdin) m1 cmout common mode voltage see description ( ad0/cs ) m0 filt+ positive voltage reference 1 2 3 4 20 19 18 17 5 6 7 8 16 15 14 13 9 10 12 11
cs4391 22 ds335pp3 serial clock - sclk pin 4, input function: clocks the individual bits of the serial data into the sdata pin. the required relationship between the left/right clock, serial clock and serial data is defined by the mode control byte in control port mode or the mode pins in hardware mode. the options are detailed in figures 6-24. left / right clock - lrck pin 5, input function: the left / right clock determines which channel is currently being input on the serial audio data input, sdata. the frequency of the left/right clock must be at the input sample rate. audio samples in left/right sample pairs will be simultaneously output from the digital-to-analog converter whereas right/left pairs will exhibit a one sample period difference. the required relationship between the left/right clock, serial clock and serial data is defined by the mode control byte in control port mode or the mode pins in stand-alone mode. the options are detailed in figures 6-24 . master clock - mclk pin 6, input function: the master clock frequency must be either 256x, 384x, 512x, 768x or 1024x the input sample rate in sin- gle speed mode; either 128x, 192x 256x, 384x or 512x the input sample rate in double speed mode; or 64x, 96x 128x, 192x or 256 x the input sample rate in quad speed mode. tables 8-10 illustrate the stan- dard audio sample rates and the required master clock frequencies. note: these clocking ratios are only available in control port mode when the mclk divide bit is enabled. mode select - m3, m2, m1 and m0 (stand-alone mode) pins 7, 8, 9 and 10 inputs function: the mode select pins, m0-m3, select the operational mode of the device as detailed in tables 11-15. mode select - m3 (control port mode) pin 7, input function: the mode select pin, m3, is not used in pcm control port mode and should be terminated to ground.
cs4391 ds335pp3 23 serial control interface clock - scl/cclk (control port mode) pin 8, input function: clocks the serial control data into or from sda/cdin. serial control data i/o - sda/cdin (control port mode) pin 9, input/output function: in i 2 c mode, sda is a data i/o line. cdin is the input data line for the control port interface in spi mode. address bit / chip select - ad0 / cs (control port mode) pin 10, input function: in i 2 c mode, ad0 is a chip address bit. cs is used to enable the control port interface in spi mode. the device will enter the spi mode at anytime a high to low transition is detected on this pin. once the device has entered the spi mode, it will remain until either the part is reset or undergoes a power-down cycle. positive voltage reference - filt+ pin 11, output function: positive reference for internal sampling circuits. external capacitors are required from filt+ to analog ground, as shown in figure 5 and . the recommended values will typically provide 60 db of psrr at 1 khz and 40 db of psrr at 60 hz. filt+ is not intended to supply external current. filt+ has a typical source impedance of 250 k w and any current drawn from this pin will alter device performance. common mode voltage - cmout pin 12, output function: filter connection for internal common mode reference voltage, typically 50% of va. capacitors must be connected from cmout to analog ground, as shown in figure 5. cmout is not intended to supply ex- ternal current. cmout has a typical source impedance of 250 k w and any current drawn from this pin will alter device performance. channel a and channel b mute control - amutec and bmutec pins 13 and 20, outputs function: the mute control pins go high during power-up initialization, reset, muting, master clock to left/right clock frequency ratio is incorrect or power-down. these pins are intended to be used as a control for an external mute circuit to prevent the clicks and pops that can occur in any single supply system. use of mute control is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops.
cs4391 24 ds335pp3 differential analog output - aoutb+, aoutb- and aouta+, aouta- pins 14, 15 and 18, 19, outputs function: the full scale differential analog output level is specified in the analog characteristics specifications table. analog ground - agnd pin 16, input function: analog ground reference. analog power - va pin 17, input function: analog power supply. typically 3 to 5 vdc.
cs4391 ds335pp3 25 6. pin description - dsd mode dsd audio data - dsd_a and dsd_b pins 3 and 4, inputs function: direct stream digital audio data is clocked into dsd_a and dsd_b via the dsd serial clock. dsd mode - dsd_mode pin 5, input function: this pin must be set to a logic 1 and m0-m2 must be properly set to access the dsd mode in hardware mode. refer to table 19. in control port mode, this pin must be set to a logic 1 and the control registers must be properly set to access the dsd mode. refer to register descriptions. master clock - mclk pin 6, input function: the master clock frequency must be either 4x, 6x, 8x or 12x the dsd data rate for 64x oversampled dsd data or 2x, 3x, 4x or 6x the dsd data rate for 128x oversampled dsd data. dsd serial clock - dsd_sclk pin 7, input function: clocks the individual bits of the dsd audio data into the dsd_a and dsd_b pins. reset rst amutec refer to pcm mode logic voltage vl aouta- refer to pcm mode channel a data dsd_a aouta+ refer to pcm mode channel b data dsd_b va refer to pcm mode dsd mode select dsd_mode agnd refer to pcm mode master clock mclk aoutb+ refer to pcm mode dsd serial clock dsd_sclk aoutb- refer to pcm mode refer to pcm mode (scl/cclk) m2 bmutec refer to pcm mode refer to pcm mode (sda/cdin) m1 cmout refer to pcm mode refer to pcm mode ( ad0/cs ) m0 filt+ refer to pcm mode 1 2 3 4 20 19 18 17 5 6 7 8 16 15 14 13 9 10 12 11
cs4391 26 ds335pp3 dif2 dif1 difo description 0 0 0 left justified, up to 24-bit data 001 i 2 s, up to 24-bit data 0 1 0 right justified, 16-bit data 0 1 1 right justified, 24-bit data 1 0 0 right justified, 20-bit data 1 0 1 right justified, 18-bit data 110reserved 111reserved table 1. digital interface formats - pcm modes dif2 dif1 difo description 0 0 0 64x oversampled dsd data with a 4x mclk to dsd data rate 0 0 1 64x oversampled dsd data with a 6x mclk to dsd data rate 0 1 0 64x oversampled dsd data with a 8x mclk to dsd data rate 0 1 1 64x oversampled dsd data with a 12x mclk to dsd data rate 1 0 0 128x oversampled dsd data with a 2x mclk to dsd data rate 1 0 1 128x oversampled dsd data with a 3x mclk to dsd data rate 1 1 0 128x oversampled dsd data with a 4x mclk to dsd data rate 1 1 1 128x oversampled dsd data with a 6x mclk to dsd data rate table 2. digital interface formats - dsd mode dem1 demo description 0 0 disabled 0 1 44.1 khz de-emphasis 1 0 48 khz de-emphasis 1 1 32 khz de-emphasis table 3. de-emphasis mode selection fm1 fm0 mode 0 0 single-speed mode (4 to 50 khz sample rates) 0 1 double-speed mode (50 to 100 khz sample rates) 1 0 quad-speed mode (100 to 200 khz sample rates) 1 1 direct stream digital mode table 4. functional mode selection soft zero mode 0 0 changes to affect immediately 0 1 zero cross enabled 1 0 soft ramp enabled 1 1 soft ramp and zero cross enabled table 5. soft cross or zero cross mode selection
cs4391 ds335pp3 27 atapi4 atapi3 atapi2 atapi1 atapi0 aouta aoutb 00000 mute mute 00001 mute br 00010 mute bl 00011 mute b[(l+r)/2] 00100 ar mute 00101 ar br 00110 ar bl 00111 ar b[(l+r)/2] 01000 al mute 01001 al br 01010 al bl 01011 al b[(l+r)/2] 01100 a[(l+r)/2] mute 01101 a[(l+r)/2] br 0 1 1 1 0 a[(l+r)/2] bl 0 1 1 1 1 a[(l+r)/2] b[(l+r)/2] 10000 mute mute 10001 mute br 10010 mute bl 10011 mute [(bl+ar)/2] 10100 ar mute 10101 ar br 10110 ar bl 10111 ar [(al+br)/2] 11000 al mute 11001 al br 11010 al bl 11011 al [(al+br)/2] 11100 [(al+br)/2] mute 11101 [(al+br)/2] br 11110 [(bl+ar)/2] bl 1 1 1 1 1 [(al+br)/2] [(al+br)/2] table 6. atapi decode binary code decimal value volume setting 0000000 0 0 db 0010100 20 -20 db 0101000 40 -40 db 0111100 60 -60 db 1011010 90 -90 db table 7. digital volume control
cs4391 28 ds335pp3 note:these clocking ratios are only available incontrol port mode when the mclk divide bit is enabled. sample rate (khz) mclk (mhz) see note 256x 384x 512x 768x 1024x 32 8.1920 12.2880 16.3840 24.5760 32.7680 44.1 11.2896 16.9344 22.5792 33.8688 45.1584 48 12.2880 18.4320 24.5760 36.8640 49.1520 table 8. single speed (4 to 50 khz sample rates) common clock frequencies sample rate (khz) mclk (mhz) see note 128x 192x 256x 384x 512x 64 8.1920 12.2880 16.3840 24.5760 32.7680 88.2 11.2896 16.9344 22.5792 33.8688 45.1584 96 12.2880 18.4320 24.5760 36.8640 49.1520 table 9. double speed (50 to 100 khz sample rates) common clock frequencies sample rate (khz) mclk (mhz) see note 64x 96x 128x 192x 256x 176.4 11.2896 16.9344 22.5792 33.8688 45.1584 192 12.2880 18.4320 24.5760 36.8640 49.1520 table 10. quad speed (100 to 200 khz sample rates) common clock frequencies m3 m1 (dif1) m0 (dif0) description format figure 00 0 left justified, up to 24-bit data 06 00 1 i 2 s, up to 24-bit data 17 01 0 right justified, 16-bit data 28 01 1 right justified, 24-bit data 39 table 11. single speed (4 to 50 khz) digital interface format, stand-alone mode options m3 m2 (dem) description figure 00 no de-emphasis 12 01 de-emphasis enabled 12 table 12. single speed only (4 to 50 khz) de-emphasis, stand-alone mode options m3 m2 m1 m0 description format figure 1000 left justified up to 24-bit data 06 1001 i 2 s up to 24-bit data 17 1010 right justified 16-bit data 28 1011 right justified 24-bit data 39 table 13. double speed (50 to 100 khz) digital interface format, stand-alone mode options
cs4391 ds335pp3 29 m3 m2 m1 m0 description format figure 1100 left justified up to 24-bit data 06 1101 i 2 s up to 24-bit data 17 1110 right justified 16-bit data 28 1111 right justified 24-bit data 39 table 14. quad speed (100 to 200 khz) digital interface format, stand-alone mode options dsd_mode m2 m1 m0 description 1000 64x oversampled dsd data with a 4x mclk to dsd data rate 1001 64x oversampled dsd data with a 6x mclk to dsd data rate 1010 64x oversampled dsd data with a 8x mclk to dsd data rate 1011 64x oversampled dsd data with a 12x mclk to dsd data rate 1100 128x oversampled dsd data with a 2x mclk to dsd data rate 1101 128x oversampled dsd data with a 3x mclk to dsd data rate 1110 128x oversampled dsd data with a 4x mclk to dsd data rate 1111 128x oversampled dsd data with a 6x mclk to dsd data rate table 15. direct stream digital (dsd), stand-alone mode options
cs4391 30 ds335pp3 figure 6. format 0, left justified up to 24-bit data lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 figure 7. format 1, i 2 s up to 24-bit data lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 lrck sclk left channel right channel sdata 6543210 987 15 14 13 12 11 10 6543210 987 15 14 13 12 11 10 32 clocks figure 8. format 2, right justified 16-bit data figure 9. format 3, right justified 24-bit data lrck sclk left channel sdata 6543210 7 23 22 21 20 19 18 6543210 7 23 22 21 20 19 18 32 clocks 0 right channel
cs4391 ds335pp3 31 lrck sclk left channel right channel sdata 6543210 987 15 14 13 12 11 10 10 6543210 987 15 14 13 12 11 10 17 16 17 16 32 clocks 19 18 19 18 figure 10. format 4, right justified 20-bit data. (available in control port mode only) lrck sclk left channel right channel sdata 6543210 987 15 14 13 12 11 10 10 6543210 987 15 14 13 12 11 10 17 16 17 16 32 clocks figure 11. format 5, right justified 18-bit data. (available in control port mode only) gain db -10db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183 khz 10.61 khz figure 12. de-emphasis curve ss a channel volume control aouta aoutb left channel audio data right channel audio data b channel volume control mute mute figure 13. atapi block diagram
cs4391 32 ds335pp3 7. applications 7.1 recommended power-up sequence for hardware mode 1) hold rst low until the power supplies, master, and left/right clocks are stable. 2) bring rst high. 7.2 recommended power-up sequence and access to control port mode 1) hold rst low until the power supply, master, and left/right clocks are stable. in this state, the control port is reset to its default settings and cmout will remain low. 2) bring rst high. the device will remain in a low power state with cmout low and the con- trol port is accessible. 3) write 11h to register 5 within 10 ms cycles fol- lowing the release of rst . 4) the desired register settings can be loaded while keeping the pdn bit set to 1. 5) set the pdn bit to 0 which will initiate the pow- er-up sequence which requires approximately 10 s. 7.3 analog output and filtering the application note design notes for a 2-pole filter with differential input discusses the sec- ond-order butterworth filter and differential to sin- gle-ended converter which was implemented on the cs4391 evaluation board, cdb4391. the cs4391 filter, as seen in figure 14, is a linear phase design and does not include phase or amplitude compensa- tion for an external filter. therefore, the dac sys- tem phase and amplitude response will be dependent on the external analog circuitry. amutec aouta+ gnd c43 10uf gnd gnd gnd 1.18k r17 nc 4 3 2 1 con_rca_ra j3 2 3 1 2sc2878 q1 2k r25 3 1 2 q3 mmun2111lt1 12 hdr8 hdr1x2 aouta va+3/+5 r20 560 3 1 2 q4 mmun2211lt1 r24 5.62k r5 47k r28 5.62k 1.18k r18 5.62k r15 5.62k r26 c49 .1uf v- v+ + - 4 8 1 2 3 u11 mc33078d c48 .1uf gnd gnd gnd gnd gnd gnd c42 10uf cog 2700pf c7 cog 560pf c6 cog c5 560pf cog 2700pf c14 vcc vee aouta- figure 14. cs4391 output filter
cs4391 ds335pp3 33 8. control port interface the control port is used to load all the internal set- tings of the cs4391. the operation of the control port may be completely asynchronous to the audio sample rate. however, to avoid potential interfer- ence problems, the control port pins should remain static if no operation is required. the control port has 2 modes: spi and i 2 c, with the cs4391 operating as a slave device in both modes. if i 2 c operation is desired, ad0/cs should be tied to va or agnd. if the cs4391 ever detects a high to low transition on ad0/cs after power-up, spi mode will be selected. the control port registers are write-only in spi mode. 8.1 spi mode in spi mode, cs is the cs4391 chip select signal, cclk is the control port bit clock, cdin is the in- put data line from the microcontroller and the chip address is 0010000. all signals are inputs and data is clocked in on the rising edge of cclk. figure 15 shows the operation of the control port in spi mode. to write to a register, bring cs low. the first 7 bits on cdin form the chip address, and must be 0010000. the eighth bit is a read/write in- dicator (r/w ), which must be low to write. the next 8 bits form the memory address pointer (map), which is set to the address of the register that is to be updated. the next 8 bits are the data which will be placed into the register designated by the map. see table 16. the cs4391 has map auto increment capability, enabled by the incr bit in the map register. if incr is 0, then the map will stay constant for suc- cessive writes. if incr is set to 1, then map will auto increment after each byte is written, allowing block reads or writes of successive registers. 8.2 i 2 c mode in i 2 c mode, sda is a bi-directional data line. data is clocked into and out of the part by the clock, scl, with the clock to data relationship as shown in figure 3. there is no cs pin. pin ad0 forms the partial chip address and should be tied to va or agnd as required. the upper 6 bits of the 7-bit ad- dress field must be 001000. to communicate with the cs4391 the lsb of the chip address field, which is the first byte sent to the cs4391, should match the setting of the ad0 pin. the eighth bit of the address byte is the r/w bit (high for a read, low for a write). if the operation is a write, the next byte is the memory address pointer, map, which se- lects the register to be read or written. the map is then followed by the data to be written. if the op- eration is a read, then the contents of the register pointed to by the map will be output after the chip address. the cs4391 has map auto increment capability, enabled by the incr bit in the map register. if incr is 0, then the map will stay constant for suc- cessive writes. if incr is set to 1, then map will auto increment after each byte is written, allowing block reads or writes of successive registers. for more information on i 2 c, please see the i2c- bus specification: version 2.0, listed in the ref- erences section.
cs4391 34 ds335pp3 76543210 incr reserved reserved reserved reserved map2 map1 map0 00000000 incr (auto map increment enable) default = 0. 0 - disabled 1 - enabled map0-2 (memory address pointer) default = 000. table 16. memory address pointer (map) map msb lsb data byte 1 byte n r/w map = memory address pointer address chip cdin cclk cs 0010000 figure 15. control port timing, spi mode sda scl 001000 addr ad0 r/w start ack data 1-8 ack data 1-8 ack stop note: if operation is a write, this byte contains the memory address pointer, map. note 1 figure 16. control port timing, i 2 c mode
cs4391 ds335pp3 35 -0.25 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0.25 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 frequency (normalized to fs) amplitude db figure 17. single-speed frequency response figure 18. single-speed transition band figure 19. single-speed transition band figure 20. single-speed stopband rejection -0.25 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0.25 0 0.050.1 0.150.20.250.30.350.40.450.5 frequency (normalized to fs) amplitude db figure 21. double-speed frequency response figure 22. double-speed transition band
cs4391 36 ds335pp3 figure 23. double-speed transition band figure 24. double-speed stopband rejection
cs4391 ds335pp3 37 9. parameter definitions total harmonic distortion + noise (thd+n) the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10hz to 20khz), including distortion components. expressed in decibels. dynamic range the ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dbfs signal. 60 db is then added to the resulting measurement to refer the measurement to full scale. this technique ensures that the distortion components are below the noise level and do not effect the measurement. this measurement technique has been accepted by the audio engineering so- ciety, aes17-1991, and the electronic industries association of japan, eiaj cp-307. interchannel isolation a measure of crosstalk between the left and right channels. measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. units in decibels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain error the deviation from the nominal full scale analog output for a full scale digital input. gain drift the change in gain value with temperature. units in ppm/c. 10. references 1. "how to achieve optimum performance from delta-sigma a/d & d/a converters" by steven harris. paper presented at the 93rd convention of the audio engineering society, october 1992. 2. cdb4391 evaluation board datasheet 3. the i 2 c-bus specification: version 2.0 philips semiconductors, december 1998. http://www.semiconductors.philips.com
cs4391 38 ds335pp3 11. package dimensions notes: 1. d and e1 are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. dimension b does not include dambar protrusion/intrusion. allowable dambar protrusion shall be 0.13 mm total in excess of b dimension at maximum material condition. dambar intrusion shall not reduce dimension b by more than 0.07 mm at least material condition. 3. these dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. inches millimeters not e dim min nom max min nom max a -- -- 0.043 -- -- 1.10 a1 0.002 0.004 0.006 0.05 -- 0.15 a2 0.03346 0.0354 0.037 0.85 0.90 0.95 b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3 d 0.252 0.256 0.259 6.40 6.50 6.60 1 e 0.248 0.2519 0.256 6.30 6.40 6.50 e1 0.169 0.1732 0.177 4.30 4.40 4.50 1 e -- -- 0.026 -- -- 0.65 l 0.020 0.024 0.028 0.50 0.60 0.70 0 4 8 0 4 8 jedec #: mo-153 controlling dimension is millimeters. 20l tssop (4.4 mm body) package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view
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